Changeset 3094

Timestamp:

07/06/06 23:16:36

Author:

matt

Message:

added DC-offset compensation

Files:

• import/usrp-svnrepository-20060801/trunk/fpga/toplevel/mrfm/mrfm.qsf (modified) (3 diffs)
• import/usrp-svnrepository-20060801/trunk/fpga/toplevel/mrfm/mrfm.v (modified) (1 diff)

import/usrp-svnrepository-20060801/trunk/fpga/toplevel/mrfm/mrfm.qsf

@@ -233 +233 @@
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-FF
-FF
-FF
+N
+N
+N
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
@@ -370 +370 @@
-
-
-FF
+N
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name VERILOG_FILE mrfm.vh
@@ -409 +409 @@
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

import/usrp-svnrepository-20060801/trunk/fpga/toplevel/mrfm/mrfm.v

@@ -124 +124 @@
-     adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0};
-
+   wire [15:0] adc0_corr;
+   rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr),
+        .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0));
+
-   //wire [63:0] filt_debug = 64'd0;
-   
-   mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
-                       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-
+_corr
-                       .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out),
-                       .debugbus( /* filt_debug */ ));