root/gnuradio/trunk/usrp/firmware/src/usrp2/eeprom_init.c

Revision 6044 (checked in by eb, 1 year ago)

Updated license from GPL version 2 or later to GPL version 3 or later.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
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1 /* -*- c++ -*- */
2 /*
3  * Copyright 2004 Free Software Foundation, Inc.
4  *
5  * This file is part of GNU Radio
6  *
7  * GNU Radio is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 3, or (at your option)
10  * any later version.
11  *
12  * GNU Radio is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with GNU Radio; see the file COPYING.  If not, write to
19  * the Free Software Foundation, Inc., 51 Franklin Street,
20  * Boston, MA 02110-1301, USA.
21  */
22
23 #include "usrp_common.h"
24 #include "usrp_commands.h"
25 #include "spi.h"
26
27 /*
28  * the host side fpga loader code pushes an MD5 hash of the bitstream
29  * into hash1.
30  */
31 #define   USRP_HASH_SIZE      16
32 xdata at USRP_HASH_SLOT_0_ADDR unsigned char hash0[USRP_HASH_SIZE];
33
34
35 #define enable_codecs() USRP_PA &= ~(bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B)
36 #define disable_all()   USRP_PA |=  (bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B)
37
38 static void
39 write_byte_msb (unsigned char v);
40
41 void
42 write_both_9862s (unsigned char header_lo, unsigned char v)
43 {
44   enable_codecs ();
45
46   write_byte_msb (header_lo);
47   write_byte_msb (v);
48
49   disable_all ();
50 }
51
52 // ----------------------------------------------------------------
53
54 static void
55 write_byte_msb (unsigned char v)
56 {
57   unsigned char n = 8;
58   do {
59     v = (v << 1) | (v >> 7);    // rotate left (MSB into bottom bit)
60     bitS_OUT = v & 0x1;
61     bitS_CLK = 1;
62     bitS_CLK = 0;
63   } while (--n != 0);
64 }
65
66 // ----------------------------------------------------------------
67
68 #define REG_RX_PWR_DN            1
69 #define REG_TX_PWR_DN            8
70 #define REG_TX_MODULATOR        20
71
72 void eeprom_init (void)
73 {
74   unsigned short counter;
75   unsigned char  i;
76
77   // configure IO ports (B and D are used by GPIF)
78
79   IOA = bmPORT_A_INITIAL;       // Port A initial state
80   OEA = bmPORT_A_OUTPUTS;       // Port A direction register
81
82   IOC = bmPORT_C_INITIAL;       // Port C initial state
83   OEC = bmPORT_C_OUTPUTS;       // Port C direction register
84
85   IOE = bmPORT_E_INITIAL;       // Port E initial state
86   OEE = bmPORT_E_OUTPUTS;       // Port E direction register
87
88   EP0BCH = 0;                   SYNCDELAY;
89
90   // USBCS &= ~bmRENUM;         // chip firmware handles commands
91   USBCS = 0;                    // chip firmware handles commands
92
93   USRP_PC &= ~bmPC_nRESET;      // active low reset
94   USRP_PC |=  bmPC_nRESET;
95
96   // init_spi ();
97   bitS_OUT = 0;                 /* idle state has CLK = 0 */
98
99   write_both_9862s (REG_RX_PWR_DN,    0x01);
100   write_both_9862s (REG_TX_PWR_DN,    0x0f);    // pwr dn digital and analog_both
101   write_both_9862s (REG_TX_MODULATOR, 0x00);    // coarse & fine modulators disabled
102
103   // zero firmware hash slot
104   i = 0;
105   do {
106     hash0[i] = 0;
107     i++;
108   } while (i != USRP_HASH_SIZE);
109
110   counter = 0;
111   while (1){
112     counter++;
113     if (counter & 0x8000)
114       IOC ^= bmPC_LED0;
115   }
116 }
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