root/gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v

`include "math_real.v"

module chan_fifo_readers_test();
    
    // Inputs
    reg reset;
    reg txclock;
    reg [31:0] datain;
    reg [31:0] ttime;
    reg WR;
    reg adcclock;
    reg debug;
    reg WR_done;
    wire [15:0] tx_q;
    wire [15:0] tx_i;
    wire underrun;

    reg [15:0] i ;
    reg [15:0] phase ;

    // fifo inputs
    wire skip;
    wire rdreq;
   
    // fifo ouputs
    wire [31:0] fifodata;
    wire pkt_waiting;
    wire tx_strobe;
    wire tx_empty;
    
    math math ( ) ;
    
    reg [15:0] siga ;
    reg [15:0] sigb ;
    
    chan_fifo_reader chan0 (
        .reset              (reset),
        .tx_clock           (txclock),
        .adc_time           (ttime),
        .skip               (skip),
        .rdreq              (rdreq),
        .pkt_waiting        (pkt_waiting),
        .fifodata           (fifodata),
        .tx_q               (tx_q),
        .tx_i               (tx_i),
        .underrun           (underrun),
        .samples_format     (4'd0),
        .tx_empty           (tx_empty),
        .tx_strobe          (tx_strobe) 
    );
    
    
    // Channel fifo
    channel_ram tx_data_fifo (  
        .reset              (reset),
        .txclk              (txclock), 
        .datain             (datain),
        .WR                 (WR),
        .have_space         (),
        .dataout            (fifodata),
        .packet_waiting     (pkt_waiting),
        .RD                 (rdreq),
        .WR_done            (WR_done), 
        .RD_done            (skip)
    );
    
    strobe_gen strobe_generator (
        .reset              (reset),
        .enable             (1'b1),
        .clock              (txclock),
        .strobe_in          (1'b1),
        .strobe             (tx_strobe),
        .rate               (8'd3) 
    );

    initial begin
        // Setup the initial conditions
        reset = 1;
        adcclock = 0;
        txclock = 0;
        datain = 0;
        WR = 0;
        i = 0 ;
        ttime = 0;
        debug = 0;
        WR_done = 0;
        phase = 0 ;
      
        // Deassert the reset
        #40 reset = 1'b0 ;

        // Wait a few clocks
        repeat (5) begin
          @(posedge txclock)
            reset = 1'b0 ;
        end
        
        send_packet(9'd128, 2'd2, 32'h00000300) ;
        send_packet(9'd128, 2'd0, 32'hFFFFFFFF) ;
        send_packet(9'd128, 2'd1, 32'hFFFFFFFF) ;
        send_packet(9'd128, 2'd3, 32'hFFFFFFFF) ;
        
    end
   
    always@(posedge adcclock) begin
        ttime <= ttime + 1;
    end
    
    always
          #5 txclock = ~txclock ;
    
    always
          #5 adcclock = ~adcclock ;
    
    task send_packet;
        input [8:0]length;
        input [1:0] flag;
        input [31:0] timestamp;
        reg [8:0] newlength ;
        begin
            i = 0 ;
            newlength = 4*(length-2) ;
            repeat (length) begin
                @(posedge txclock) begin
                    WR = 1;
                    if ( i == 0) 
                        datain = {3'd0, flag, 18'd0, newlength} ;
                    else if ( i == 1) 
                        datain = timestamp;
                    else begin
                        siga = math.round(math.sin(4*phase*`MATH_DEG_TO_RAD)*(math.pow(2,15)-1)) ;
                        sigb = math.round(math.cos(phase*`MATH_DEG_TO_RAD)*(math.pow(2,15)-1)) ;
                        phase = phase + 1 ;
                        datain = {siga,sigb} ;
                    end
                    i = i + 1 ;
                end
            end
            
            if (length < 128) begin
                @(posedge txclock)
                    WR_done = 1;
                    WR = 0;
                @(posedge txclock)
                    WR_done = 0;
            end
            else begin
                @(posedge txclock)
                    WR = 0;
            end
        end
    endtask

endmodule