= USRP FPGA =

The FPGA being used on the [wiki:USRP USRP] is an [http://www.altera.com Altera] [http://www.altera.com/products/devices/cyclone/cyc-index.jsp Cyclone EP1C12Q240C8].

Features of the EP1C12:

	LEs		12,060
	M4k RAM blocks (128 x 36 bits)		52
	Total RAM bits		239,616
	PLLs		2
	Maximum user I/O pins		173

The hardware language used to describe the functionality within the FPGA is written in [http://en.wikipedia.org/wiki/Verilog Verilog] and synthesized using Altera's free web tool [http://www.altera.com/products/software/products/quartus2/qts-index.html Quartus II]. It should be noted that Quartus II can run free only within a Windows environment, though there are ways to [wiki:QuartusUnderLinux run Quartus II under Linux] without the need for Windows - YMMV.

The FPGA runs off a 64MHz clock with every internal component synchronous to that global clock. Due to the relatively high clocking frequency, everything within the FPGA is highly to achieve the highest speed possible.

Receive Chain
Describe the receive chain within the FPGA. Link to the way the [http://www.analog.com/en/prod/0,,AD9862,00.html AD9862 MxFE] is controlled and how the filters in that component is controlled. SVG visual aides helpful.

AD9862 -> CORDIC -> Decimating CIC Filter (4 stage, Programmable decimation rate) -> Halfband Decimation Filter (Fixed decimation by 2) -> RX FIFO

Transmit Chain
Describe the transmit chain within the FPGA. Link to the way the [http://www.analog.com/en/prod/0,,AD9862,00.html AD9862 MxFE] is controlled and how the filters in that component is controlled. SVG visual aides helpful.

TX FIFO -> Interpolating CIC Filter (4 stage, Programmable interpolation rate) -> CORDIC -> AD9862

USB Interface
Describe how the host communicates with the [http://gnuradio.org/trac/wiki/USRP USRP] device.

=== Register Definitions ===
Any registers that can be set or read within the FPGA should be listed out here along with hardware read/write addresses.

Daughtercard Control
How to write to the USB interface to control things such as frequency tuning or filtering. Message Block
Describe or link to the [http://gnuradio.org/trac/wiki/MessageBlock message block component] of the FPGA allowing for tightly timed transmit and receive functionality.