=== Any hints for getting started? In particular, what needs to be done to talk to the usrp2 via the ethernet? ===

The first step is to update to the latest svn for the entire gnuradio tree, and get it all installed. Then, run find_usrps in the usrp2/host/apps directory. You'll need to tell it which ethernet port to use if the USRP2 is not on eth0. The program should tell you if it found USRP2s.

=== What is a good basic app to test the USRP2 ===

Run

{{{
usrp2_fft.py
}}}
which is found in gr-utils and should also be installed in your path if you did a make install on the full tree. This will give you a basic spectrum analyzer display. Run {{{
usrp2_fft.py -h
}}}
for a list of options.

=== How do I compile the firmware for the aeMB RISC processor? ===

You will need to build a gcc toolchain first. Follow the directions at http://www.aeste.net/index.php?q=node/16

=== Can you also provide details concerning the debug port? ===

The debug port is a standard Mictor connector which is often used with logic analyzers from Agilent and Tektronix. It has 2 clock pins and 32 data pins. All 34 of those are directly connected to the FPGA, so you can do whatever you want with them.

If you plug in a BasicRX (or LFRX) and a BasicTX (or LFTX), you will have an additional 32 bits of IO which can also be used for debugging. This gives a total of 64 bits plus 2 clocks for debug.

=== Is there a JTAG port? ===

Yes, there is a standard JTAG header on the board connected to the FPGA and a CPLD, but you may not need it. Since the FPGA is programmed from the SD Card by the bootstrapping CPLD, the main utility of the JTAG port is to reprogram the CPLD. You may be able to use the JTAG port with !ChipScope.

=== I would like to interface to the expansion port, and connect the USRP2 to a Virtex 5 SXT eval board. I am looking for any documentation concerning this port, especially how it is tied into the the FPGA, if that is the case. ===

The expansion port is pretty straightforward. It uses a serial-attached SCSI (mini-SAS) cable. The cable has 4 lanes. Each lane consists of 1 differential pair input and 1 differential pair output. All lanes are AC (capacitor) coupled. The 4 lanes are allocated as follows:

1 - High-speed SERDES, 2 gbps 8B10B encoded. This interface is handled by a TLK2701 from TI, and it connects to the FPGA. You should be able to connect this interface to the RocketIO GTP/GTX transceivers on the virtex 5. Also, see the usrp2/fpga/serdes directory in the SVN repository to see how we handle the interface and protocol, framing, and flow control.

2 - 10 MHz clock reference

3 - Digital IO, connected directly to LVDS IOs on the FPGA. We currently have this set up to do time syncing, but you can do whatever you like with it.

4 - Unused