- What are the differences between the USRP1 and USRP2?
- What FPGA is used in the USRP2?
- I know that the USRP2 does not support two transceivers. But does it support 2 coherent receivers?
- Can I compile FPGA designs with the free version of the Xilinx tools?
- What are the different ways MIMO can be set up with more than one USRP2?
- What is the use of the 1 PPS and 10 MHz inputs? These are standard outputs of a GPS unit. Are they external references or are they are used in the Ethernet time stamping?
- Is the timestamp only tied to (t=0 to) the 1PPS-pulse? I hope to use faster sync pulse like at 1-10kHz, and get the timestamp referenced to them. Is this possible?
- What are the electrical specifications for the 10MHz reference signal?
- What are the electrical specifications for the PPS input?
- What phase relation do you expect between 10MHz and 1PPS?
- What is the 1 Megabyte SRAM used for?
- How are the connections between USRP2 boxes intended to work? There are a MIMO connector and an frequency reference input.
- Is it possible to connect more boxes together using the MIM0 connector?
- Where is the limitation of 8 antennas as stated on the datasheet?
- How can I use both A/D converters on the USRP2?
- Does the external frequency reference have to be 10 MHz? Can I use 100 MHz?
- Can an external clock be used instead of the internal 100 MHz VCXO?
- What is the Job of 10MHz Reference Clock ?
- What chipset is used in the USRP2 for managing the Gigabit Ethernet interface?
- How does the USRP2 boot? How is the FPGA firmware loaded?
- What is the USRP2 ADC chip? Is there an auxiliary ADC?
- What is the USRP2 DAC chip? Is there an auxiliary DAC?
- Is there auxiliary Digital I/O?
- How are the USRP2 DDCs implemented ? How many CIC stages does it contain?
- How are the USRP2 DUCs implemented ? How many CIC stages does it contain?
- What does the magnitude response of the low rate HBF interpolator look like?
- And what about the low rate HBF decimator?
- What is the magnitude response of the high rate HBF interpolator/decimator?
- How is the USRP2 HBF for TX and RX sides are implemented?
- What are the USRP2 minimum and maximum decimation/interpolation values? Is odd decimation/interpolation possible?
- How are the USRP2 DACs fed ?
- What are the default USRP2 IP address and subnet mask?
- Does USRP2 respond to a network ping command?
- What is the USRP2 reference clock stability?
- With the BasicTX board, the USRP1 can generate a maximum of 44 MHz frequency. What is the USRP2 capable of generating?
- What is the USRP2 overrun message?
- What is the USRP2 underrun message?
- What are the most important (hot) trunk USRP2 code that we need to check to understand USRP2 architecture, configuration, and operation?
- How much of the USRP2's FPGA resources are required by the FPGA firmware?
- What is the serial setting needed to talk to the USRP2's UART (Baudrate, parity,...etc) ?
- Is the processing of set_scale_iq done in the host or in the FPGA?
- What is the purpose of the AeMB processor? What is its clocking speed?
- Where is the USRP2's MAC address stored ?
- What is the meaning of each LED on the USRP2?
What are the differences between the USRP1 and USRP2?¶
|Interface||USB 2.0||Gigabit Ethernet|
|FPGA||ltera EP1C12||Xilinx Spartan 3 2000|
|RF Bandwidth to/from host||8 MHz @ 16bits||25 MHz @ 16bits|
|ADC Samples||12-bit, 64 MS/s||14-bit, 100 MS/s|
|DAC Samples||14-bit, 128 MS/s||16-bit, 400 MS/s|
|Daughterboard capacity||2 TX, 2 RX||1 TX, 1 RX|
|Power||6V, 3A||6V, 3A|
What FPGA is used in the USRP2?¶
XC3S2000-5FGG456, That is the Spartan 3 2000, fast speed grade (-5), 456 pin BGA package.
I know that the USRP2 does not support two transceivers. But does it support 2 coherent receivers?¶No, a single USRP2 can only support either
- 1 RX and 1 TX daughterboard.
- 1 Transceiver daughterboard
You would need two USRP2s linked with a MIMO cable in order to have 2 coherent receivers. The exception is if you use your own external RF downconverters, in which case you can connect two of them to one BasicRX.
Can I compile FPGA designs with the free version of the Xilinx tools?¶
Please note that the USRP2 uses a Spartan 3-2000 chip. This means that if you intend to do your own FPGA development, you need to use the full version of the Xilinx tools in order to generate an image for it. You cannot use the free web pack version. Thus there are several options for you:
- Just use the prebuilt FPGA images we provide
- Purchase the full version of ISE from Xilinx
- Get a 60 day demo version from the Xilinx Web Site
- Convince your Xilinx apps engineer to get you a free copy
- Universities often get the tools free of charge
- Release your changes to the community and we can find some sort of way to build them for you (if anybody wants to work on putting together some scripts to do this automatically, let me know).
What are the different ways MIMO can be set up with more than one USRP2?¶
There are 3 things necessary to get MIMO working.
1. All systems need to be phase-locked to a common clock (10 MHz in this case)
2. All systems need to have a common time reference (often a 1 PPS signal) so that they know which sample in one system corresponds to which sample in the other
3. All the data needs to come from / go to the same place
The MIMO Expansion interface on the USRP2 carries all 3 of those.
Scenario 1 - Two USRP2 systems connected by a MIMO cable:
The Master USRP2 is the one connected to both ethernet and the MIMO cable.
The Slave USRP2 is the one connected to just the MIMO cable.
The master provides a clock to the slave over the MIMO cable.
The master provides the time reference to the slave over the MIMO cable.
On transmit, the host sends all data over the ethernet to the master.
The master uses the data which is intended for the master, and passes the data for the slave over the MIMO cable.
On receive, the slave sends all data over the MIMO cable to the master, and the master passes it back to the host over ethernet. It also sends its own data over the ethernet to the host.
The firmware and host driver code to do this is not ready yet, but is in progress. (14 November 2008)
Scenario 2 - Up to Four USRP2 systems connected by MIMO cables to the not-yet-in-existence HUB:
The HUB has a big FPGA on it.
The HUB provides clock and time reference to all USRP2 systems.
The HUB communicates with the host computer by ethernet or PCI Express, or operates standalone.
All USRP2 systems send data back and forth to the HUB.
The HUB is not ready yet, but the design is in progress. We hope to have it ready in 9-12 months. (14 November 2008)
Scenario 3 - An arbitrary number of USRP2 systems, no MIMO cables, no HUB:
Some means of providing the same 10 MHz reference to all USRP2 systems must be set up. Typically this would be the 10 MHz output of some lab reference like a GPS-locked reference. That reference would be put through some sort of active splitter, and fed into all the USRP2s by SMA connector on the front panel.
Some means of providing the same time reference to all USRP2 systems is also needed. This would normally be a 1 PPS signal generated by the same reference. It will need to go through some sort of active splitter and send into the PPS input of all the USRP2 systems.
ALL the USRP2 systems will need to be connected to the host computer by gigabit ethernet. You can probably use an ethernet switch, but there will be issues with sharing the bandwidth.
The firmware to do this is ready. The host code to do it is not ready yet. (14 November 2008)
What is the use of the 1 PPS and 10 MHz inputs? These are standard outputs of a GPS unit. Are they external references or are they are used in the Ethernet time stamping?¶
The USRP2 uses a 100 MHz clock internally. That clock will be locked to the 10 MHz reference you provide.
Samples can be time stamped, and that time can be calibrated to the 1 PPS signal. In the most general case, that 1 PPS input just goes directly to the FPGA, so internally you can do whatever you want with it.
Is the timestamp only tied to (t=0 to) the 1PPS-pulse? I hope to use faster sync pulse like at 1-10kHz, and get the timestamp referenced to them. Is this possible?¶
The 1 PPS input goes to an FPGA pin, so you can program the FPGA to do whatever you want. This includes accepting faster sync pulses, encoded timestamps, Morse code, etc.
What are the electrical specifications for the 10MHz reference signal?¶
The Reference input can take a square or sine wave input that is DC-blocked and terminated in 50 ohms. The input should be less than 3V pk-pk.
What are the electrical specifications for the PPS input?¶
The PPS input is not DC blocked. It is AC terminated in 50 ohms, DC terminated in 1K ohms. The digital signal you put in should be between 0 and 5 V. It should never go below 0V and never above 6V.
What phase relation do you expect between 10MHz and 1PPS?¶
The PPS signal should be synchronous to the 10 MHz reference. Nearly any GPS frequency reference should work. Everything from http://jackson-labs.com would suffice.
What is the 1 Megabyte SRAM used for?¶
In the standard FPGA build we provide right now, it isn't used at all. One could set it up for a number of different uses:
- Large buffers to hold pre-modulated packets, like ACK packets
- A very large FIFO to hold bursts of samples at rates higher than what the Ethernet would normally allow
- An auxiliary RAM for either data or instructions (or both) for the RISC processor
All of the above would require some Verilog coding on your part.
How are the connections between USRP2 boxes intended to work? There are a MIMO connector and an frequency reference input.¶
The MIMO connector brings the frequency reference from one USRP2 to the other. If you wish to use an external frequency reference to lock both USRP2s, you would feed it to the first USRP2, and the MIMO connector will deliver it to the 2nd.
Is it possible to connect more boxes together using the MIM0 connector?¶
Not directly. Eventually, we will be selling another device to allow you to connect more than 2 USRP2s together (most likely 4), but for now you would be limited to 2.
Where is the limitation of 8 antennas as stated on the datasheet?¶
How can I use both A/D converters on the USRP2?¶
Usually the 2 are used for I and Q from the downconverters, but you can use them separately as well by using the BasicRX.
Does the external frequency reference have to be 10 MHz? Can I use 100 MHz?¶
Actually, you can use 100 MHz as well, you will just need to change one line of the firmware to set the R-divider on the PLL. You can use any frequency for which the following equation has a solution:
100 MHz / N = Ref / R for which N and R are integers and smaller than 32,768
Can an external clock be used instead of the internal 100 MHz VCXO?¶
The internal clock (a very clean VCXO) is locked to the external reference if one is applied. You have a lot of flexibility in selecting the reference frequency (see previous question), but you cannot pull the VCXO further than a few kHz, and you cannot use the reference as the main system clock. So there is no way, for example, to put in a 120 MHz clock and have everything run off of that. You are basically stuck with 100 MHz unless you are willing to solder.
If you are willing to do some soldering, there are pin-compatible VCXOs in other frequencies which are available. The part is the CVHD950 from Crystek, and you can get them from Mouser. Note than anything over 100 MHz may make it hard to get the FPGA to meet timing requirements. Also, the ADC is only specified to 105 MHz, but there is a pin-compatible version spec'ed to 125 MHz.
What is the Job of 10MHz Reference Clock ?¶
The 10 MHz reference input on the front is optional. If you connect it and enable locking, the 100 MHz main oscillator will lock to it, otherwise it will free run. Everything inside the FPGA runs at 100 MHz (DSP) or 50 MHz (processor).
There is also a 10 MHz reference clock sent out on the MIMO connector. When turned on, it will be the 100 MHz clock divided down by 10.
What chipset is used in the USRP2 for managing the Gigabit Ethernet interface?¶
It's done with an open source MAC implemented in the FPGA and a National Semicondutor PHY chip, DP83856.
How does the USRP2 boot? How is the FPGA firmware loaded?¶
The CPLD (a Xilinx XC9572) reads the first megabyte from the SD card and
writes it to the FPGA config pins in slave-serial mode. Once the FPGA is
configured, it requests the firmware for the aeMB processor from the SD
card. After that, the CPLD is switched over to passthru mode, and the
FPGA has direct access to the SD card under program control.
What is the USRP2 ADC chip? Is there an auxiliary ADC?¶
The main ADC is the Dual 14-bit LTC2284, used at 100 MS/s. There is an auxiliary 2 channels, 12-bit
ADC (the AD7922) for each dboard connector.
What is the USRP2 DAC chip? Is there an auxiliary DAC?¶
The main DAC is the Dual 16-bit AD9777 fed with 100 Ms/s and produces 400 Ms/s based analog output. The auxiliary DACs are the dual 12-bit AD5623.
Is there auxiliary Digital I/O?¶
The same USRP1 16 digital IOs, SPI, and I2C to each daughterboard connector. The whole interface to the daughterboards is the same as the USRP1, except instead of it being implemented all in the AD9862, it is done with the following set:
- 2x AD5623
- 2x AD7922
How are the USRP2 DDCs implemented ? How many CIC stages does it contain?¶
The DDCs are very similar to the USRP1 with a 4 stage CIC but with 2 HBF filters. The CIC can decimate in the range [1..128]. The high rate HBF has 7 taps and it decimates by 2. The low rate HBF has 31 taps and also decimates by 2.
How are the USRP2 DUCs implemented ? How many CIC stages does it contain?¶
Again, very similar. There us a 4 stage CIC and 2 HBF filters each working in interpolation mode.
What does the magnitude response of the low rate HBF interpolator look like?¶
And what about the low rate HBF decimator?¶
It is identical to the one of the interpolator, see above.
What is the magnitude response of the high rate HBF interpolator/decimator?¶
How is the USRP2 HBF for TX and RX sides are implemented?¶
I will explain the RX side, the TX side is basically the same.
small_hb_dec is the short filter which works at the higher rate. There are 2 of them instantiated, one for I and one for Q. It has 7 taps. One of those taps is the center tap which only requires a shift and not a multiply, and 2 of those taps are zeros. That leaves 4 taps. The taps are symmetric, which leaves 2 multiplies per output. Since we have at least 2 cycles to produce each output, we can use a single multiplier.
hb_dec is 2nd halfband filter and it works at the lower rate. There are 2 of them instantiated, one for I and one for Q. It has 31 taps. One of those taps is the center tap which only requires a shift and not a multiply, and half of the remainder are zeros. That leaves 16 taps. They are symmetric, so that means we need to do 8 multiplies to produce each output. There are at least 4 cycles to produce each output, so we need to do 2 multiplies at a time.
One of those multipliers does the "outer" coefficients, meaning the ones at the very beginning and end of the impulse response, and one does the "inner" coefficients, meaning the ones around the center of the impulse response. This division is purely an implementation choice, and does not affect the output. I could have put the odd ones on one mult and the even ones on the other, or any other split you could imagine. It doesn't matter.
What are the USRP2 minimum and maximum decimation/interpolation values? Is odd decimation/interpolation possible?¶
Minimum interpolation and decimation is 4 and maximum is 512. If you use odd decimation or interpolation, you just get a CIC with no halfbands. If you use an even rate but not a multiple of 4, you just get one halfband (the low rate one). If your rate is a multiple of 4, you use both halfbands.
How are the USRP2 DACs fed ?¶
The FPGA talks to the DAC at 100 MS/s just like it talks to the ADC at 100 MS/s. The interpolation from 100 MS/s to 400 MS/s happens inside the DAC chip itself. Unless you are doing something fancy, you can think of the
DAC as operating at 100 MS/s.
The primary reason for the x4 interpolation to 400 MS/s is to simplify the analog reconstruction filters. It also allows for a coarse modulation up to 150 MHz, but I don't anticipate that being used very often.
What are the default USRP2 IP address and subnet mask?¶
The standard USRP2 FPGA image does not use IP, just raw ethernet.
Does USRP2 respond to a network ping command?¶
No, but we have our own, find_usrps
What is the USRP2 reference clock stability?¶
About 20 ppm unless you lock to an external reference.
With the BasicTX board, the USRP1 can generate a maximum of 44 MHz frequency. What is the USRP2 capable of generating?¶
44 MHz is the highest frequency in the first Nyquist zone on the USRP1.
Much higher frequencies can be used in the higher zones. The USRP2 takes 100 MS/s rates and interpolates up to 400 MS/s. Direct
frequencies up to ~170 MHz should be usable. The code that initializes the DAC is in u2_init.c
What is the USRP2 overrun message?¶
Currently, overruns are shown on the UART port and not on the host. They
are shown with a "O". The reality is that you should never see them.
If the host computer can't keep up, you will see an "S" messages in the
terminal on the host that indicates a sequence number error.
What is the USRP2 underrun message?¶
Under runs are shown on the UART port as "U".
What are the most important (hot) trunk USRP2 code that we need to check to understand USRP2 architecture, configuration, and operation?¶
In the FPGA code, the tx_control.v and rx_control.v show inband
signalling, dsp_core_rx and dsp_core_tx show the DSP, and u2_core.v is
the top level. In the firmware, start with txrx.c.
How much of the USRP2's FPGA resources are required by the FPGA firmware?¶
37 out of 40 block RAMs, 16 or 18 of the 40 multipliers, and about 35 to
40% of the logic area.
What is the serial setting needed to talk to the USRP2's UART (Baudrate, parity,...etc) ?¶
The serial is TTL level with 230400 baud, 8N1 format
Is the processing of set_scale_iq done in the host or in the FPGA?¶
The scaling itself is done in the DSP pipeline in the FPGA.
The aeMB processor is a fully synthesized CPU that forms the heart of
the USRP2 FPGA system-on-a-chip design. It performs configuration and
status reporting for all the FPGA peripherals, manages the control
channel for the GbE transport, and handles RF daughterboard operation.
It does not perform any DSP functions; these are done purely in logic
in the DSP RX and TX pipelines. It is clocked at 50 MHz, half the
system clock rate.
Where is the USRP2's MAC address stored ?¶
The USRP2's MAC address is stored on the USRP2's motherboard EEPROM.
What is the meaning of each LED on the USRP2?¶
At start-up, all 6 LEDs will flash and 2 will remain ON. The bottom one shows that the FPGA is configured. The next one up shows that the firmware is running. The others are unused.