# Copyright (C) 1991-2007 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions 

# and other software and tools, and its AMPP partner logic 

# functions, and any output files from any of the foregoing 

# (including device programming or simulation files), and any 

# associated documentation or information are expressly subject 

# to the terms and conditions of the Altera Program License 

# Subscription Agreement, Altera MegaCore Function License 

# Agreement, or other applicable license agreement, including, 

# without limitation, that your use is for the sole purpose of 

# programming logic devices manufactured by Altera and sold by 

# Altera or its authorized distributors.  Please refer to the 

# applicable agreement for further details.

# The default values for assignments are stored in the file

#		spiMaster_assignment_defaults.qdf

# If this file doesn't exist, and for assignments not listed, see file

#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C20Q240C8

set_global_assignment -name TOP_LEVEL_ENTITY spiMaster

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2

set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:18  FEBRUARY 21, 2008"

set_global_assignment -name LAST_QUARTUS_VERSION 7.2

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace

set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240

set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBus_h.v

set_global_assignment -name VERILOG_FILE ../rtl/ctrlStsRegBI.v

set_global_assignment -name VERILOG_FILE ../rtl/dpMem_dc.v

set_global_assignment -name VERILOG_FILE ../rtl/fifoRTL.v

set_global_assignment -name VERILOG_FILE ../rtl/initSD.v

set_global_assignment -name VERILOG_FILE ../rtl/readWriteSDBlock.v

set_global_assignment -name VERILOG_FILE ../rtl/readWriteSPIWireData.v

set_global_assignment -name VERILOG_FILE ../rtl/RxFifo.v

set_global_assignment -name VERILOG_FILE ../rtl/RxFifoBI.v

set_global_assignment -name VERILOG_FILE ../rtl/sendCmd.v

set_global_assignment -name VERILOG_FILE ../rtl/spiCtrl.v

set_global_assignment -name VERILOG_FILE ../rtl/spiMaster.v

set_global_assignment -name VERILOG_FILE ../rtl/spiMaster_h.v

set_global_assignment -name VERILOG_FILE ../rtl/spiTxRxData.v

set_global_assignment -name VERILOG_FILE ../rtl/timescale.v

set_global_assignment -name VERILOG_FILE ../rtl/TxFifo.v

set_global_assignment -name VERILOG_FILE ../rtl/TxFifoBI.v

set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBI.v

set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"