Revision a98e5bc7 usrp2/fpga/extram/extram_wb.v

b/usrp2/fpga/extram/extram_wb.v
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   wire     write_acc = stb_i & cyc_i & we_i;
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   wire     acc = stb_i & cyc_i;
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   assign   RAM_CLK = wb_clk;   // 50 MHz for now, eventually should be 200 MHz








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   assign   RAM_CLK = ~wb_clk;   // 50 MHz for now, eventually should be 200 MHz







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   assign   RAM_LDn = 0;        // No burst for now







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   assign   RAM_CENn = 0;       // Use CE1n as our main CE







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......




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     else







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       case(RAM_state)







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	 RAM_idle :







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	   if(read_acc)








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	   if(read_acc & ~ack_o)







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	     begin







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		RAM_state <= RAM_read_1;







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		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0;







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	     end







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	   else if(write_acc)








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	   else if(write_acc & ~ack_o)







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	     begin







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		RAM_state <= RAM_write_1;







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		myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0;







......




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	 RAM_write_1 : 







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	   begin







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	      RAM_state <= RAM_write_2;







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	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1;








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	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1;







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	   end







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	 RAM_write_2 : 







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	   begin







......




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   assign     RAM_CE1n = ~RAM_EN;    // Active low     (RAM_state != RAM_idle);







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   assign     RAM_D[17:16] = 2'bzz;







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   assign     RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_3)?ram_out[15:0]:ram_out[31:16]) 








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   assign     RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) 







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	      : 16'bzzzz_zzzz_zzzz_zzzz;







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   always @(posedge wb_clk)











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