root / usrp2 / fpga / testbench / PAUSE.sav @ 253018c6
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| 1 | [size] 1400 967 |
|---|---|
| 2 | [pos] -1 -1 |
| 3 | *-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
| 4 | [treeopen] u2_sim_top. |
| 5 | [treeopen] u2_sim_top.u2_basic. |
| 6 | [treeopen] u2_sim_top.u2_basic.MAC_top. |
| 7 | [treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. |
| 8 | @22 |
| 9 | u2_sim_top.GMII_TXD[7:0] |
| 10 | @28 |
| 11 | u2_sim_top.GMII_TX_EN |
| 12 | @200 |
| 13 | - |
| 14 | @24 |
| 15 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] |
| 16 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] |
| 17 | @28 |
| 18 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en |
| 19 | @22 |
| 20 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] |
| 21 | @28 |
| 22 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst |
| 23 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk |
| 24 | @24 |
| 25 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] |
| 26 | @28 |
| 27 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk |
| 28 | @200 |
| 29 | - |
| 30 | @28 |
| 31 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen |
| 32 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete |
| 33 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int |
| 34 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 |
| 35 | @200 |
| 36 | - |
| 37 | @28 |
| 38 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen |
| 39 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete |
| 40 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int |
| 41 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 |
| 42 | @200 |
| 43 | - |
| 44 | @28 |
| 45 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply |
| 46 | @22 |
| 47 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] |
| 48 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] |
| 49 | @28 |
| 50 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub |
| 51 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val |
| 52 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 |
| 53 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 |
| 54 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst |
| 55 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk |
| 56 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en |
| 57 | u2_sim_top.u2_basic.proc_int |
| 58 | @22 |
| 59 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] |
| 60 | u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] |
| 61 | @25 |
| 62 | u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] |