root / usrp / fpga / sdr_lib / atr_delay.v @ 11376fc8
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| 1 | // -*- verilog -*- |
|---|---|
| 2 | // |
| 3 | // USRP - Universal Software Radio Peripheral |
| 4 | // |
| 5 | // Copyright (C) 2007 Corgan Enterprises LLC |
| 6 | // |
| 7 | // This program is free software; you can redistribute it and/or modify |
| 8 | // it under the terms of the GNU General Public License as published by |
| 9 | // the Free Software Foundation; either version 2 of the License, or |
| 10 | // (at your option) any later version. |
| 11 | // |
| 12 | // This program is distributed in the hope that it will be useful, |
| 13 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | // GNU General Public License for more details. |
| 16 | // |
| 17 | // You should have received a copy of the GNU General Public License |
| 18 | // along with this program; if not, write to the Free Software |
| 19 | // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA |
| 20 | // |
| 21 | |
| 22 | module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o); |
| 23 | input clk_i; |
| 24 | input rst_i; |
| 25 | input ena_i; |
| 26 | input tx_empty_i; |
| 27 | input [11:0] tx_delay_i; |
| 28 | input [11:0] rx_delay_i; |
| 29 | output atr_tx_o; |
| 30 | |
| 31 | reg [3:0] state; |
| 32 | reg [11:0] count; |
| 33 | |
| 34 | `define ST_RX_DELAY 4'b0001 |
| 35 | `define ST_RX 4'b0010 |
| 36 | `define ST_TX_DELAY 4'b0100 |
| 37 | `define ST_TX 4'b1000 |
| 38 | |
| 39 | always @(posedge clk_i) |
| 40 | if (rst_i | ~ena_i) |
| 41 | begin |
| 42 | state <= `ST_RX; |
| 43 | count <= 12'b0; |
| 44 | end |
| 45 | else |
| 46 | case (state) |
| 47 | `ST_RX: |
| 48 | if (!tx_empty_i) |
| 49 | begin |
| 50 | state <= `ST_TX_DELAY; |
| 51 | count <= tx_delay_i; |
| 52 | end |
| 53 | |
| 54 | `ST_TX_DELAY: |
| 55 | if (count == 0) |
| 56 | state <= `ST_TX; |
| 57 | else |
| 58 | count <= count - 1; |
| 59 | |
| 60 | `ST_TX: |
| 61 | if (tx_empty_i) |
| 62 | begin |
| 63 | state <= `ST_RX_DELAY; |
| 64 | count <= rx_delay_i; |
| 65 | end |
| 66 | |
| 67 | `ST_RX_DELAY: |
| 68 | if (count == 0) |
| 69 | state <= `ST_RX; |
| 70 | else |
| 71 | count <= count - 1; |
| 72 | |
| 73 | default: // Error |
| 74 | begin |
| 75 | state <= `ST_RX; |
| 76 | count <= 0; |
| 77 | end |
| 78 | endcase |
| 79 | |
| 80 | assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY); |
| 81 | |
| 82 | endmodule // atr_delay |
| 83 |