Feature #66

Implement closed loop AGC for USRP1

Added by Eric Blossom over 6 years ago. Updated over 1 year ago.

Status:Rejected Start date:
Priority:Normal Due date:
Assignee:Matt Ettus % Done:

0%

Category:-
Target version:to-be-decided
Resolution:

Description

We need to implement a few types of AGC, and have them run a sufficiently tight control loop. We should accept input from all or any of these inputs:
  • RSSI on RFX cards
  • Post-ADC / Pre-DDC power levels
  • Post DDC power levels
    We should control the gain using the strategies implemented in the daughterboard code. I.e., controlling gain on the d'board if possible and/or the AD9862 Rx PGA.

We should also look at implementing these in the FPGA, with the current gain/level reported in-band across the USB.

History

Updated by Johnathan Corgan over 6 years ago

Milestone post-release-3.0 deleted

Updated by Johnathan Corgan over 6 years ago

Milestone release-3.2 deleted

Updated by Matt Ettus over 1 year ago

  • Status changed from New to Rejected

Will be done in UHD.

Also available in: Atom PDF