Feature #363
Implement closed loop AGC for USRP2
| Status: | Closed | Start date: | ||
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Johnathan Corgan | % Done: | 0% |
|
| Category: | unknown | |||
| Target version: | release-3.3-series | |||
| Resolution: | wontfix |
Description
Implement AGC loop in USRP2 FPGA/firmware as Wishbone peripheral with the following modes of operation:
- Adjust gain as need to maintain constant average power
- Track steady state power or hold at existing gain based on logic signal
- Manual gain setting
History
Updated by Tom Rondeau over 1 year ago
- Status changed from New to Resolved
- Resolution set to wontfix
Removing USRP from tree; replacing with UHD.
Updated by Tom Rondeau over 1 year ago
- Status changed from Resolved to Closed